Iri Trashanski, Chief Strategy Officer at Ceva, is shaping the future of the Smart Edge with extensive experience across tech ...

Next generation semiconductor design puts new stress on traditionally low-key parts of the design process. One example is ...

The relentless march towards shrinking technology nodes has ushered in a new era of intricate semiconductor designs ...

Sondrel, a leading provider of ultra-complex custom chips, has announced that it has started front end, RTL design and ...

Frontgrade Gaisler has launched its latest radiation-hardened microcontroller, the GR716B. Building on the success of the ...

Designers of aerospace and defense systems know that their applications are mission-critical and demand the highest levels of ...

Cadence has announced a groundbreaking achievement with the development and successful tapeout of its first Arm-based system ...

Traditional interconnects have been unable to deliver the bandwidth, latency, and power efficiency needs of hyperscale data ...

HBM implementation challenges This is the second in a three-part series from Alphawave Semi on HBM4 and gives insights into ...

FlexNoC 5 interconnect IP with physical awareness improves place and route efficiency and reduces interconnect area and power ...

TSMC is looking to introduce its A16 1.6nm process by the end of 2026 with an IEEE standard for its 3Dblox technology.

Xiphera’s board of five includes company’s co-founders and three other people from different backgrounds. The new board is filled with new kind of ...