Design-Reuse51m
Timing Optimization Technique Using Useful Skew in 5nm Technology Node
The relentless march towards shrinking technology nodes has ushered in a new era of intricate semiconductor designs ...
Design-Reuse2d
HPC customer engages Sondrel for high end chip design
Sondrel, a leading provider of ultra-complex custom chips, has announced that it has started front end, RTL design and ...
Design-Reuse2d
Power Deliver Network Monitoring and Droop Detection
The Aeonic Insight™ Droop Detector is used as part of the Movellus Integrated Droop Response System, comprising of the Aeonic Insight Droop Detector and the Aeonic Generate™ AWM3. In combination, ...
Design-Reuse3d
Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
Semiconductor veterans secure $3.7M seed funding to launch a universal RISC-V processor that eliminates the need for ...
Design-Reuse3d
Redefining XPU Memory for AI Data Centers Through Custom HBM4 - Part 2
HBM implementation challenges This is the second in a three-part series from Alphawave Semi on HBM4 and gives insights into ...
Design-Reuse3d
Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
Frontgrade Gaisler has launched its latest radiation-hardened microcontroller, the GR716B. Building on the success of the ...
Design-Reuse4d
World's First CXL 3.1 Multi-Vendor Interoperability Demo Showcases New Memory Possibilities for Hyperscale Data Centers
Traditional interconnects have been unable to deliver the bandwidth, latency, and power efficiency needs of hyperscale data ...
Design-Reuse4d
Die-to-Die PHY
Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging types (including advanced packaging and standard ...
Design-Reuse5d
CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Panmnesia, a South Korean fabless CXL startup, announced that it has successfully secured over $60M in Series A funding.
Design-Reuse5d
Cadence Unveils Arm-Based System Chiplet
Cadence has announced a groundbreaking achievement with the development and successful tapeout of its first Arm-based system ...
Design-Reuse5d
Streamlining SoC Design with IDS-Integrate™
System-on-chip (SoC) designers face significant challenges when integrating thousands of IP blocks from various vendors, ...
Design-Reuse5d
TSMC drives A16, 3D process technology
TSMC is looking to introduce its A16 1.6nm process by the end of 2026 with an IEEE standard for its 3Dblox technology.